1. Field of the Invention
The present invention relates to a structure and method for forming a controllably variable resistor having wide application to a variety of unique digital and analog circuits, including both programmable digital integrated circuit devices, and programmable analog integrated circuit devices.
The present invention even more particularly relates to a structure and method for forming and setting a programmable resistive element such as a fuse or antifuse used in programming digital integrated circuit devices including redundant memory elements, for example. This invention also relates to a programmable or trimming resistor used in analog RF circuit tuning applications. More specifically, this disclosure relates to a structure and method for non-ablatively forming a fuse, antifuse, or trimming resistor element without ablation by selectively altering resistivity of the variable resistor to a finite value.
2. Description of Related Art
The continued progress in improving integrated circuit (IC) performance, either by device scaling or by more efficient utilization of chip area, is directed to allowing faster and smaller devices to be manufactured, as well as to allowing a reduction in manufacturing process time and expense, both during manufacture of the semiconductor device itself, as well as during the testing of the device.
Traditionally, programmable devices or devices incorporating redundant circuitry are manufactured to provide end-user flexibility in the ultimate application of the device, and/or to increase production yield. Applications, which often use such redundant circuitry or programmable elements, include, for example, programmable logic arrays (PLA) or dynamic random access memory (DRAM) devices.
Fuses are employed in integrated circuits to encode or xe2x80x9cprogramxe2x80x9d information on a circuit chip at the time of manufacture. A fusible link, or xe2x80x9cfusexe2x80x9d, is one that provides a closed or low resistance connection when first formed, and which is modified to provide an open or high resistance circuit when programmed.
The encoded information is used to later identify the chip, to enable or tune circuits depending on test results, or to repair defective regions of the chip by enabling spare or redundant circuits. The redundant circuitry can be selectively removed from the final device configuration by the use of fusible conductive links, or fuses.
In the case of fusible conductive links, an ablative approach is often used to provide flexibility and improve production yield. However, there is an area penalty incurred on the chip by the inclusion of the redundant circuitry, and damage may result to the surrounding circuitry.
The typical method for providing fuses is to form small conductive paths that can be selectively ablated with a precisely positioned laser beam, or by providing a current that is high enough to melt the conductive material. Such, ablation of the conductive link encodes the necessary information as a series of bits, or selectively enables or disables one or more circuits in the integrated circuit. A drawback with this method is that the area required by the region damaged by ablation is relatively large, so that features and devices cannot be fabricated near the fuses. Another drawback with laser-ablated fuses is that they do not scale well with lithography.
The ablative damage associated with such a fuse blowing process typically extends at least a few microns around the fuse, and often extends into the top few layers of the so-called xe2x80x9cback-end-of-the-linexe2x80x9d (BEOL) structure. BEOL processing, also known in the industry as xe2x80x9cback endxe2x80x9d, generally is considered to include steps from contact to the semiconductor substrate through completion of the wafer, prior to electrical test. Structure resulting from back-end processing may include, for example, addition of insulating or conductive material, e.g., Copper (Cu) used in high performance processors, and dielectric insulators such as silicon dioxide.
The damage to such back-end structures poses reliability concerns, such as the electrical shorting of elements that the manufacturer does not intend to be shorted. Damage resulting from blowing fuses also imposes limits on the proximity of adjacent fuses, and hence fuse pitch reduction which directly affects circuit packing density, and which may be cumulative to the area penalty imposed by the inclusion of the redundant circuitry. Typical fuse pitches are limited to the range of 3 to 10 xcexcm, are conventionally available, with a fuse pitch of greater than 3 xcexcm being common in processes that open or xe2x80x9cblowxe2x80x9d the fusible links ablatively.
The damage and debris that occurs around the programmed link after ablation can limit the achievable pitch in manufacturing the device and, consequently, the level of integration and miniaturization. Therefore, both the ultimate scalability and reliability of the device are necessarily affected adversely by conventional approaches to programming a fuse. The technology used for integrated circuit manufacturing is migrating to low k and ultra low k materials which are mechanically very weak and very susceptible to damage from disruptive fuse programming like ablation. Non-ablative fuses can play an important role for advanced CMOS interconnect technology.
The use of fusible links for device personalization has further inherent limitations. Specifically, the fuse link can only be blown open or left closed; they cannot be used to close a previously opened link. Personalization where a previously open connection is made closed requires another approach.
Redundant circuitry can be selectively added to the final device configuration by the use of antifusible links, or xe2x80x9cantifusesxe2x80x9d, which are structures that, when first fabricated, are an open or high resistance circuit. When the antifuse is xe2x80x9cprogrammedxe2x80x9d the open circuit becomes closed, and conduction across the antifuse becomes possible. Thus, antifuses are used to perform the opposite and complementary function of a fuse.
In the case of either using a fuse or antifuse to program a device, making such discretionary connections alters the function or operating characteristics of integrated circuits. Typically, when a sufficient voltage called a xe2x80x9cfusing voltagexe2x80x9d is applied across an antifuse structure, the resulting current flow and energy imparted into the fuse element causes the structure to change into an electrically conductive state, or become permanently shorted, and an electrical connection is made. Antifuses are also used in a wide variety of applications, including Field Programmable Gate Arrays (FPGA).
Conventional antifuse technology has several disadvantages. For example, many conventional antifuses require specific metal types to be used as electrodes. These metals are not always compatible with common fabrication technologies. For example, some conventional approaches require a transparent electrode, and thus cannot use electrodes consisting of aluminum or polysilicon, which are opaque. Furthermore, these antifuse structures generally require 12-15 volts to fuse the antifuse. Applying such a voltage to the antifuse can also cause damage to other circuit elements, and thus these antifuses may be incompatible with modem low-voltage semiconductor devices that commonly operate at 3.3 volts or 2.5 volts. Additionally, these structures will be difficult to scale to the significantly smaller sizes that will be required as semiconductor device density increases, for similar reasons to those noted with respect to fuse pitch reduction limits imposed by ablative damage to adjacent BEOL structure.
In other applications, for example, radio frequency (RF) integrated circuit applications, impedance matching between devices and circuits is very important to ensure that a low VSWR is attained, so that proper operation of the circuits can be maintained. As various semiconductor devices are usually incorporated into such an RF integrated circuit, the interactions between the various signals present and the numerous devices can be complex, and correcting for the various device impedances to match to a conductive signal path through the device can be challenging.
Trim resistors which require laser trimming or cutting are often employed, but such trimming techniques pose the same problems in terms of area penalty and damage to surrounding structure from the ablation of the conductive material as in the case of a digital programmable element.
Therefore, what is needed then is an improved structure and method for forming a variable resistor element which reduces processing time and which improves reliability. What is further needed is a non-ablative structure and method for varying a resistor element""s value in applications, which, for example, program a fuse element, or to match impedance, and which reduces or eliminates the damage imposed upon surrounding structure. What is still further needed is a structure and method for programming a variable resistor element, which has improved reliability, and which allows fuse and antifuse elements or other circuitry to be positioned on a tighter pitch, thereby reducing the chip area penalty incurred by redundant circuitry or impedance matching or trimming resistors.
The present invention solves the aforementioned problems relating to maintaining the reliability of back-end structure, as well as preventing damage of adjacent structures and hence enabling the reduction the required fuse pitch and area penalty associated with variable resistors used as fuses or antifuses to select or deselect redundant circuitry, as well as the problems associated with adjusting impedance trimming resistors.
A new method and structure for forming a variable resistor and non-ablatively adjusting or trimming a resistance value of the variable resistor has been discovered. The process is non-ablative, as opposed to traditional laser or current ablative techniques, so that reliability of the device is improved. The process is also cleaner than conventional ablative approaches, and the elimination of damage to the surrounding area allows the fuses or resistive elements to be positioned on a tighter pitch, thereby reducing the penalty in area required for redundant circuitry, or for trimming resistors.
In one embodiment of the invention, a non-ablative method of programming an integrated circuit device includes providing a programmable element including at least two conductive materials, and changing a resistance of the programmable element to a finite value. The resistance of the programmable element may be changed by heating the programmable element by providing a current flow through the programmable element, or by directing a laser beam onto the programmable element. The current flow may be pulsed, and the number of current pulses applied may be used to determine the resistance of the programmable element. The current flow may also be regulated, or a voltage may be applied across the programmable element. Alternatively, the programmable element could be heated by focusing an ion beam, molecular beam or an electron beam onto the programmable element.
By heating the programmable element to a sufficient degree, the combination of conductive materials may be interdiffused to form an alloy of the conductive materials, which may be, for example, Cu and Ni, which also may be laminated. In addition, more than two conductive materials may be laminated. For example, a layer of Ni could be sandwiched between two layers of Cu.
The conductive materials used are not limited to Cu and Ni and may be, for example, a lamination of at least one pair of materials selected from the group consisting of Cuxe2x80x94Ni, Auxe2x80x94Pd, Auxe2x80x94Pt, and Auxe2x80x94Cu. Also, one of the conductive materials could include a layer of Si, which could be doped, or could be amorphous or polycrystalline silicon.
The resistance of the programmable element may be changed to a finite value that may be increased or decreased relative to an initial value. The resistance may be changed by less than an order of magnitude relative to the initial resistance of the programmable element, or the resistance of the programmable element may be changed to a finite value that is more than an order of magnitude different relative to the initial resistance of the programmable element. Precise resistance change can be guaranteed by tailoring the thickness of the metal layers, because the final composition of the fuse is a function of the thickness ratio of the starting layers. Since the change in resistance is an order of magnitude, the amount of time required for the associated electrical circuitry to sense the resistive logic state of the programmable element can be made small, and hence programming or setting of the resistance value may be accomplished faster than is conventionally achievable.
In another aspect of this embodiment, a reference resistance element having a resistance approximately equal to an initial resistance of the programmable element is provided. The programmable element may have an initial resistance that is within 50% of a resistance value of the reference resistance element, and the resistance of the programmable element may be changed to a finite value which is decreased by at least an order of magnitude relative to the initial resistance of the programmable element.
In another embodiment, a programmable integrated circuit device includes a bistable element, a variable resistance coupled to the bistable element, and switching means for switching an output state of the bistable element in response to a sensed resistance value of the variable resistance. While the programmable integrated circuit device is in a pre-programmed state, the variable resistance may be a laminate structure two or more conductive materials.
When the programmable integrated circuit device is in a programmed state, the variable resistance may be an interdiffusion of at least two conductive materials, which may be an isomorphous solid solution of at least two conductive materials, or may be an alloy of at least two conductive materials. As in the first embodiment, the two or more conductive materials may include Cu and Ni, or the conductive materials may include at least two materials selected from the group consisting of Cu, Ni, Al, Ti, W, Pd, Pt, Au, Ag, and Si.
A programmed resistance value of the variable resistance may be greater than an initial resistance value of the variable resistance by at least an order of magnitude, or the programmed resistance value of the variable resistance may be greater than an initial resistance value of the programmable element by less than an order of magnitude.
The programmed resistance value of the variable resistance also may be less than a pre-programmed resistance value of the variable resistance by at least an order of magnitude.
In one aspect of this embodiment, the switching means may include an output circuit, a precharge device, a set device, and a read device. The output circuit may be a complementary output circuit, or it may be a single output circuit.
In this embodiment, a reference resistance having a resistance approximately equal to an initial resistance of the programmable element may also be coupled to the bistable element.
In another embodiment, a method of programming a programmable integrated circuit device is disclosed for a programmable integrated circuit device which includes a bistable element, a programmable element including a lamination of at least two conductive materials coupled to the bistable element, a reference resistor coupled to the bistable element which has a resistance value approximately equal to an initial resistance value of the programmable element, an output circuit, a precharge device, a set device, and a read device, wherein a programmed state of the programmable integrated circuit device is determined by a resistance value of the programmable element. The above method includes increasing an initial resistance of the programmable element by approximately an order of magnitude by interdiffusing the lamination of the at least two conductive materials, triggering the set device, latching a data value representing the programmed state into the bistable element, triggering the read device, and reading the programmed state from the bistable element through the output circuit.
Similar to the earlier discussed embodiments, interdiffusing the lamination of the at least two conductive materials may include forming an alloy of Cu and Ni.
In yet another embodiment, a variable resistor is disclosed which includes a resistive element which includes a first conductive material and a second conductive material in contact with the first conductive material. A resistance of the variable resistor is determined at least in part by a relative amount of the second conductive material with respect to an amount of the first conductive material in the resistive element. The resistive element may include a lamination of the first conductive material and the second conductive material. In addition, the resistive element may further include a third conductive material in contact with said second conductive material. The lamination may have the second conductive material sandwiched between the first conductive material and the third conductive material. The first and third conductive materials may be the same type of material. As in the earlier discussed embodiments, the first and second conductive materials may be Cu and Ni, respectively.
Alternatively, the first and second conductive materials may be selected from the group consisting of Cu, Ni, Al, Ti, W, Pd, Pt, Au, Ag, and Si. The variable resistor may have a resistive element which is an alloy of the first and second conductive materials, or an alloy of the first, second, and third conductive materials.
In another embodiment, a method of forming a variable resistor is disclosed which includes providing a first conductive material, providing a second conductive material, and interdiffusing the first and second materials. Interdiffusing may include forming an alloy of the first and second conductive materials.
Controlling a programmed resistance value of the variable resistor may be accomplished, at least in part, by providing the second conductive material in a specified amount relative to the first conductive material, and the first and second conductive materials may be laminated initially. The first and second conductive materials may then be interdiffused by heating. Heating may be accomplished by, for example, either providing an electrical current through the first and second conductive materials, or by non-ablatively exposing a laser beam on the first and second conductive materials.
A second portion of the first conductive material may also be placed in contact with the second conductive material. This may be accomplished by, for example, by laminating the second portion of the first conductive material, the first conductive material, and the second conductive material.
In another embodiment of the invention, a resistance trimming device is disclosed which includes a bi-layer resistive element having a first conductive layer on a second conductive layer, a pair of programming transistors, wherein a first transistor of the pair is arranged between a first voltage and a first end of the bi-layer resistive element. A second transistor of the pair may be arranged between a distal end of the bi-layer resistive element and a second voltage. The first and second transistors may conduct a current through the bi-layer resistive element sufficient to interdiffuse at least a portion of the first conductive layer with the second conductive layer in response to a programming signal applied to each of the first and second transistors.
A trimmed resistance value of the bi-layer resistive element may be determined by a value of the current and the time duration of the programming signal. The current may be a pulsed current, and the number of current pulses provided may determine the trimmed resistance value of the bi-layer resistive element.
In another aspect of this embodiment, a plurality of pairs of programming transistors is provided. Each pair of programming transistors may be connected to the bi-layer resistive element at different respective locations than the first and second transistors. A trimmed resistance value of the bi-layer resistive element may be determined by respective values of a plurality of currents through associated pairs of programming transistors, and time durations of the respective programming signals.
As in previously discussed embodiments, the first conductive layer and the second conductive layer may be Cu and Ni, respectively, or may be pairs of previously mentioned conductive materials.